What is CuTe layout algebra?

CUTLASS's layout algebra and C++ type system, where a shape and stride define a coordinate-to-index function that can be composed and divided into tiled mappings.

A CuTe Layout maps a coordinate to an integer index. Its shape bounds the coordinate space and its stride defines the map. A row-major matrix with shape (M,N) and stride (N,1) therefore maps (row,col) to row * N + col without storing or copying matrix data.

Composition combines two index maps. Division splits one map into the coordinates inside a tile and the grid of tiles. That gives CUTLASS a typed way to describe movement between global memory, shared memory and an instruction's operand layout. Layout transformations such as padding and swizzling change the map rather than scattering address arithmetic through a kernel.

Measured

On a Tesla T4 (driver 580.173.02, CUDA 12.6), day 84 checked CuTe v4.7.1 against independent arithmetic. Composition matched 12/12 published indices, zipped_divide matched 32,768/32,768 matrix indices, the divide identity matched 256/256 indices, and a device gather matched 32,768/32,768 elements.

Related terms

• CUTLASS
• tiling
• shared memory
• global memory
• padding and swizzling

Where you meet this

• Day 84, CUTLASS and CuTe layouts, which compares the algebra with day 16's hand-written indexing.
• Day 16, tiled matrix multiply, where the same coordinate map is written as integer arithmetic.

Sources

• CuTe layout documentation: https://github.com/NVIDIA/cutlass/blob/v4.7.1/media/docs/cpp/cute/01_layout.md (checked 2026-09-01)
• CuTe layout algebra: https://github.com/NVIDIA/cutlass/blob/v4.7.1/media/docs/cpp/cute/02_layout_algebra.md (checked 2026-09-01)

Byline

Written by: pending. Reviewed by: pending. Written on: pending. Last checked on: pending. Verified evidence was captured on 2026-09-02; publication still requires named author and reviewer sign-off.